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Lattice Semiconductor
CSIX Level 1 IP Core User’s Guide
Synthesis using LeonardoSpectrum
The step-by-step procedure provided below describes how to run synthesis using LeonardoSpectrum.
1. Launch the Leonardo Spectrum synthesis tool.
2. Select -> File -> Run Script
navigate to select the following ?le: eval\synthesis\exemplar\user_application\fpga_syn_001.tcl
This automatically starts the synthesis process. When complete, the resulting synthesized design resides in
the ?le: TOP.edf.
Place and Route for ORCA Series 4 Devices
Once the EDIF netlist is generated, the next step is to import the EDIF into the Project Navigator. The ispLEVER
software automatically detects the provided EDIF netlist of the instantiated IP core in the design. The step-by-step
procedure provided below describes how to perform place and route in ispLEVER for an ORCA device:
1. Copy the following ?les to the Place and Route working directory: eval\par
a) eval\ngo\csix_lev1_o4_01_001.ngo
b) eval\prf\csix_lev1_o4_01_001.prf
c) The top-level EDIF netlist generated from running synthesis
Rename the copied ?le: csix_lev1_o4_01_001.prf to TOP.prf.
2. Launch the ispLEVER software.
3. Select -> New Project
navigate to: eval\par
type in the project name: TOP
select -> Project type -> EDIF
click on the SAVE button.
4. In the project window, right click on the listed Lattice device
Select -> Select New Device
Choose -> ORCA or4e404, -2 speed, BM680 package.
5. In the project window, right click on the listed or4e04 device
Select -> Import
Choose -> TOP.edf (or TOP.edn if you used synplicity)
6. In the ispLEVER Project Navigator, select Tools ->Timing Checkpoint Options . The Timing Checkpoint
Options window will pop-up. In both Checkpoint Options, select Continue .
7. In the ispLEVER Project Navigator, highlight Place & Route Design , with a right mouse click select Proper-
ties . Set the following properties:
? Placement Iterations: 1
? Placement Save Best Run: 1
? Placement Iteration Start Point: 1
? Routing Resource Optimization: 1
? Routing Delay Reduction Passes: 5
? Routing Passes: 30
? Placement Effort Level: 5
All other options remain at their default values. The properties shown above are the settings for single channel 32-
bit mode. Each core con?guration has its own properties settings. For the appropriate settings for speci?c con?gu-
ration, please refer to the Readme.htm included in the downloaded package.
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相关PDF资料
CSIX-PI40-O4-N1
INTERFACE IP CSIX TO PI40 ORCA 4
CT0805S14BAUTOG
VARISTOR 14VRMS 0805 SMD AUTO
CT1206K17G
VARISTOR 17VRMS 1206 SMD
CTB-B-B-15
CIRCUIT BREAKER ROCKER 15A SP BK
CU3225K17AUTOG2
VARISTOR AUTO 17VRMS 3225 SMD
CU3225K250G2K1
VARISTOR STD 250VRMS 3225 SMD
CV10-RP-M-0
CONN JACK STR COAXIAL SMD
CVM50XM
MEMBER MOD PIC12C508/PIC12C509
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